TAEE 2020 Conference

"Approaching Field Programmable Gate Arrays with Deeds"

(by G.Donzellini)

I wish to thank André Vaz Fidalgo, Gustavo Ribeiro Alves, Manuel Carlos Felgueiras and Ricardo Jorge Costa (Instituto Superior de Engenharia do Porto, Portugal) for the invitation to the TAEE 2020 conference (July 8..10, 2020) as keynote speaker.

Here the presentation slides (PDF, about 6.9 MB):



Our experience in teaching a first year course of digital design shows that the introduction of Field Programmable Gate Arrays (FPGA) is advisable. Students demonstrate a better interest for the topics, if they can really verify the circuits they study and design. Traditional bread-board based prototyping is therefore replaced by FPGA programming, which is nowadays performed at professional level using Hardware Description Language (HDL). We are somehow critical of the current trend of introducing digital system with HDL. Our tool, Deeds (Digital Electronics Education and Design Suite) allows to configure FPGA boards for testing starting with traditional schematics-based entry, which is more compatible with the beginners’ skills, and overcomes the pre-requisite of some proficiency in high-level programming languages. Deeds integrates FPGA configuration and testing into its design and simulation flow, making digital design, including microprocessor programming, demonstrable through a few commercially available FPGA boards. Tutorials and projects, designed for flexibility and self-learning, open up many possibilities to hands-on experiments and introduce the basic skills on which building HDL competences later on. Deeds was developed at DITEN, University of Genoa, and it is composed of a set of simulators and a wide collection of associated learning material, covering combinational and sequential logic networks, finite state machine design, microcomputer interfacing and programming.