Flip-Flops and Registers

Giuliano Donzellini, Domenico Ponta

Analysis of a D-Latch flip-flop




Load the following D-Latch flip-flop schematic in the d-DcS, with a click on the figure:

Using the timing simulation , verify the behavior of the network. Pay attention to the two initialization inputs !Preset and !Clear. You should include all the possible combinations of the inputs D and EN, after the activation of the inputs !Preset or !Clear (a suitable test sequence is available in the Timing Diagram window).