The following device is a serial line receiver. The Finite State Machine (FSM) receives, through the input LINE, a synchronous bit stream consisting of 4-bit packets. The FSM outputs two signals (READY, ERROR) and controls the status of two SR flip-flops through S1, R1, S2 and R2.
LINE is at value “0” when no transmission occurs or between two subsequent packets (in this last case, for at least three clock cycles).
The start (1st) bit of each packet is always “1” and the stop (4th) bit should be always “0”. The second and third bits carry the information that must be transferred, respectively on U1 and U2, by properly controlling the two flip-flops. The values transferred to U1 and U2 must be maintained until a new packet has been received.
If the packet is received correctly (i.e. the stop bit is “0”) the FSM sets the output READY, otherwise it sets the output ERROR, as soon as possible. The values of READY and ERROR are maintained until a new packet is detected on LINE.
A RESET signal, not depicted in the above figure, forces the FSM to its initial state (with READY = ”1”).
You are requested to design the FSM using the d-FsM simulator, and then to simulate the behavior of the entire system using the d-DcS simulator (with the FSM imported as a component). We suggest, in the following figure, a test time sequence for the LINE input:
Next, synthesize the FSM (using JK-Pet FF) and re-draw the schematic substuiting the FSM component with the actual circuit obtained by synthesis. Verify the behavior of the entire new system using the d-DCS timing simulator (please, apply the same time sequence used before).
Please, report a few comments about the differences between the timing results (if any).