Microcomputer systems: assembly programming techniques

Giuliano Donzellini, Domenico Ponta

Emulation of an Asynchronous Serial Transmitter




In this laboratory you are guided to write a DMC8 assembly program that emulates an Asynchronous Serial Transmitter. It generates data packets as the one described in the following figure:

The data packet is composed as follows:

  1. One start bit (high);
  2. 8 data bits, D7 .. D0 (D0 ahead);
  3. One stop bit (low);
  4. Bit/Rate = 625 bits per second (Bit Time = 1,6 mS).

The next figure shows a FSM-based version of the transmitter (click on the figure to open the schematic in the d-DcS editor):

The system is composed of a bit time counter [A, highlighted in red], on the left hand side of the figure, a shift register [B, in blue, top-right], a bit counter [C, in red, on the right], and a controller [D, in brown, based on a finite state machine].

Bit Time Counter  [A]
The TX bit time counter, based on the Cnt4 component, is in charge of dividing by 16 the frequency of TX_CK (10 KHz), in order to transmit the data packet at the given bit/rate (625 b/s = 10 KHz /16): this part of a serial transmitter is sometimes referred to as baud rate generator. The counter is set up to count down cyclically; every time the outputs Q3..Q0 reach the number '0000', the output TC (terminal count) is activated, resulting in a pulse every 16 clock cycles. The cyclic activation of TC is used by the TX Controller to synchronize the transmission of each data bit at the given bit rate. LD signal presets the counter to the value '1111' (inputs P3..P0).

 Shift Register [B]
The TX shift register (based on the Univ4 and Univ8 components) serializes the parallel data (TX_DATA) on the output line TX_LINE. S1 and S0 control the register mode of operation: when the TX Controller drives S1 = S0 = '0', the register state will not change. When S1 = S0 = '1', the register loads in parallel the eight input data bits TX_D7 .. TX_D0, the Start Bit (P0 of the Univ8) and the Stop Bit (P1 of the Univ4). The unused register bits are set to '0'. Serial transmission starts when data is loaded, since the loading operation sets the Start Bit on TX_LINE. The following bits of the packet will be transmitted, one after the other, when the register will shift right (i.e. every time the TX Controller drives S1 = '0' and S0 = '1').

 Bit Counter [C]
The TX bit counter (also based on a Cnt4) counts the number of bits to be transmitted. The TX Controller initializes the counter to '1010', by setting the LD line. Every time the TX Controller activates the EN line, the count is decremented by one. The counter terminal count (TC) signals to the TX Controller that transmission has to be terminated.

 Controller [D]
The TX Controller functionality is described by the following ASM chart (click on it to open the FSM file in the d-FsM):

The !TX_GO command (GO for the FSM) starts the transmission: the first two states (a) and (b) are in charge of waiting for the pressure of the push-button ("low" when pressed) and also to activate LD, to preset all the counters. In the state (c), the activation of S0 and S1 loads the parallel data in the shift register, while EN causes the decrement of the number of bits to be transmitted. In the state (d), the controller waits for a TCB signal from the bit time counter: when it occurs (every 1,6 mS), the controller activates (e) the right shift of the data register (S1 = '0', S0 = '1') and decrement the number of bits to be transmitted (EN = '1'). When the number of bits to be transmitted becomes zero (TCN = '1'), the controller reaches state (f), where it generates the END output, to signal the transmission end. Finally, the controller returns to state (a).

You can test the circuit using the d-DcS simulator, in Animation Mode and in Timing Mode . A proper test sequence ("TX_Sequence") is available in the timing simulation window.

The previous analysis of the circuit operations will help you to implement the same functionalities with a microcomputer system, based on the DMC8. The microcomputer-based serial transmitter will look like the following schematic. Click on the figure to open the schematic into the d-DcS.

In this network, the TX_LINE is generated by the microcomputer on the bit 0 of the OD output port. Port IB is connected to the TX_DATA input lines, and port IA, on bit 0, reads the !TX_GO push-button. The OC output port generates the TX_END signal, on bit 0.

Click here to load a trace of a possible implementation of the assembly program. When finished to write and test the program in the d-McE, you'll load it in the ROM of the microcomputer and simulate the new circuit version in the d-DcS. Note that, to test the transmitter, the "TxSequence" input sequence is already available in the timing diagram.