


Design a digital circuit that converts a signed, positive, threebit number to the corresponding negative number, using two’s complement representation (e.g. +2 = '010' becomes 2 = '110'). In2 and Out2 are the sign bits.
The network checks if the input number is already negative and, in this case, it activates an error signal (Neg = '1') and copies (without changes) the input number to its outputs. Write a truth table of the converter. Compile a Kmaps for each output and write the expressions of the minimized synthesis of each output (synthesize them as twolevel ANDOR networks). Draw the schematic of the resulting network, using (as a trace for the solution) the dDcS schematic template provided here (click on the figure below). Verify the circuit behaviour through a functional simulation and a timing simulation (a suitable test sequence is available in the Timing Diagram window). 