Flip-flops and Registers

Giuliano Donzellini, Domenico Ponta

Timing analysis of a D-Latch flip-flop component




Verify the behavior of the following simple sequential network, based on a D-Latch Flip-Flop component. You can open it in the d-DcS, with a click on the figure:

Verify, using the timing simulation , the behavior of the flip-flop. Pay attention to put in evidence, in the timing diagram, the meaningful combinations of input values (a suitable test sequence is available in the Timing Diagram window).