Design of finite state machines Giuliano Donzellini, Domenico Ponta

Design and synthesis of a 3-bit up-counter for signed numbers

 v1.71

Design a 3-bits up-counter for number represented in two’s complement code, using the Finite State Machine Simulator (d-FsM). The counter should generate the sequence:

 -4 -3 -2 -1 0 +1 +2 +3 -4 ...etc.

You can use the provided ASM diagram template, where you'll find already defined the state variables X, Y, Z and the outputs Q2, Q1, Q0. In the template, two states (named 'a' and 'b'), have been also already defined. We suggest, as it is convenient in the present case, to assign the state codes equal to the outputs values (e.i. suppose X = Q2, Y = Q1 and Z = Q0).

At the Reset, we want that the counter will start from the number “-4” (Q2=1, Q1=0, Q0=0). For this reason, the 'a' state takes in this case the attribute of 'Reset' state (e.i. the 'starting' state of the FSM, at the activation of the asynchronous Reset).

Verify, using the timing simulation of the d-FsM, the correct flow of the output values and the state codes.

Given the ASM definition of the counter, synthesize it, using D-PET flip-flops. Use K-maps and write the boolean expressions of the next state and output networks. Draw and test the resulting circuit with the d-DcS, using the timing simulator .

Are the two timing diagrams (d-FsM/d-DcS) functionally equivalent?

Next, given the ASM chart of the counter, re-synthesize it with JK-PET flip-flops. As above, use K-maps and write the Boolean expressions. Draw and test the resulting circuit with the d-DcS, using the timing simulator .

Is there any functional difference respect to the D-PET synthesis?

Last, using the (d-FsM), save the previous file with another name and add an input "IN" to the counter. The input IN will control the counting direction (if IN = 0 the counter will count upward, if IN = 1 the counter will count downward).

Modify the ASM chart so that the counter will check the value of IN and, eventually, will change the counting direction, only when passing through "0" (the synthesis of the network is not requested).

Verify, using the timing simulation of the d-FsM, the correct flow of the operations.