Design of FSM-controlled digital systems

Giuliano Donzellini, Domenico Ponta

Design of a serial data processor




Design, using the Finite State Machine Simulator (Deeds-FsM), a synchronous digital system in charge of receiving and re-transmitting serial data. The received data, on the LN input, is represented by a packet of three bits, B0, B1 and B2, grouped together with a start bit (at ‘1’) and a stop bit (at ‘0’), according to the following figure:

The input LN is synchronous and it is at value '0' while the system waits for the start bit of a packet. Each bit has a fixed duration, called bit-time. In this case, the bit-time is equal to one clock cycle, and the clock positive edge samples data in the center of the bit-time.

The next figure shows the architecture of the system, where a FSM controls three external flip-flops. The E-pet flip-flops are in charge of storing temporarily the information bits received from LN (B0 is stored on Q0, B1 on Q1 and B2 on Q2 ). The system drives two output serial lines, LNA and LNB.

The system controls, at the end of the packet, the stop bit value. If it is not '0', the packet has not been received correctly: in this case the system ignores the received data, does not generate signals on the LNA and LNB outputs, and waits for a new packet (after checking that the input line LN is returned to '0').

After the reception of a valid sequence, the FSM uses the value of Q2 to select where to send the output (on LNA if Q2 = '0', or LNB if Q2 = '1'). The system re-transmits, on the line chosen, a new packet composed by a start bit at ‘1’, the Q0 and Q1 bits, a parity bit P and a stop bit at ‘0’ (see the next figure). The parity bit is computed as the EXOR of the stored information bits Q0 and Q1, and it is available to the FSM as P.

A trace of the ASM chart of the FSM component is available (click on the next figure to open it in the Deeds-FsM). The state variables X, Y, Z, W and K, the outputs LNA, LNB, E0, E1 and E2, and the inputs LN, P, Q0, Q1 and Q2 are already defined (the command allows to verify the FSM setup, and you can define a Mealy or Moore FSM model):

After the design of the ASM chart, you should verify, using the timing simulation of the Deeds-FsM, that the functionality of the FSM corresponds to specifications. The FSM should then be imported as a component on the Deeds-DcS, repeating there the timing simulation. To that purpose a schematic to be completed is available here, in which to insert the FSM. We recommend to use the schematic supplied, without modifying the input and output terminations.

In the Timing Diagram window three test sequences are available: 1) the first one produces the serial transmition on the output LNA; 2) the second one on the output LNB and 3) in the last one no transmission occurs.

Notes: 1) let us suppose that a suitable time interval elapses between two packets received on LN, so that the system could complete the transmission of data before a new packet will arrive; 2) the activation of the asynchronous !Reset will initialize the system in a state where it is waiting for a new packet.

Hint: to make the network simulation easier, it is possible to trace, in the Deeds-DcS timing diagram window, the FSM inputs and outputs, selecting them before to start the simulation. Click on the context menu of the FSM trace label, in the timing diagram. If you choose the menu item "Select Signals to Trace", the following dialog window will open:

After the signals selection, the FSM trace will be expandable, as represented in the following figure: