The task is the design of the system represented in the figure below. The input signal IN, normally at zero, receives aperiodic pulses (at the logical level one) whose durations is between one and seven clock periods.
The D-net flip-flop (upper left on the schematic) re-synchronizes the input bit sequences on the falling edge of clock. The timing diagram below shows a pulse on the IN input, whose duration is four periods of clock, and the correspondent EN output of the flip-flop.
The system measures the duration of the pulses, in terms of clock periods, and transmits the values as a serial signal on the output SER. For the measurement of pulse duration the system uses the CNT counter, whose schematic is available in the figure (a click on the image will load the schematic on the d-DcS).
In the system, the CNT counter and the state machine FSM-A are synchronized by the same clock signal. The FSM-A generates the counter asynchronous clear CL. FSM-A signals with TRG (one clock period duration) to FSM-B that the measurement is completed and the count value is available on the counter outputs Q2, Q1 and Q0. When necessary, FSM-A clears the count (signal CL). During the time in which the system is busy receiving the pulse and transmitting the serial data, FSM-A activated BSY.
FSM-B starts generating SER on reception of the command TRG. SER is composed by a start bit at '1', the pulse duration coded with the three bits Q0, Q1 and Q2 (LSB first) and a stop bit at '0' (see the following figure):
In addition, FSM-B activates ETX to inform FSM-A that trasmission on SER is over.
Last task: draw the d-DcS schematic of the whole system, using the FSM components just designed. Open with a click on the figure the schematic to be completed. A test sequence is available in the timing diagram window.
Note: gli impulsi su IN sono separati tra loro da un numero di periodi di clock sufficienti a permettere al sistema di completare la trasmissione del dato, prima che un altro impulso si presenti all’ingresso; la durata di un impulso non è mai superiore a sette periodi del clock CK.
Note: the IN pulses are separated by a number of clock periods that allow the system to complete data transmission, before another pulse appears in input; the pulse duration is never longer than seven clock periods.
Second version (extended measurement)
The figure represents a modified version of the system, able to deal with pulses up to 127 clock periods long:
The counter, available in the d-DcS library, is called Cnt8 (see the symbol in the following figure). A description of Cnt8 behavior is available here.
Cnt8 has the same function as Cnt in the previous circuit. The count value is available on the outputs Q6 .. Q0 (Q7 is not used). Remaining system specifications are the same, as well as the FSM-A, while FSM-B differs only by the number of bits generated on SER. As visible in the figure, there are seven data bits:
Design and simulate, using d-FsM, the new FSM-B (here the trace of the ASM chart). Last, complete the schematic of the modified system opening it by clicking on the figure below. A test sequence is available in the timing diagram window.