Design the binary comparator shown in the figure. The comparator receives two numbers A and B (coded as two-bits binary numbers, on the inputs A1,A0 and B1,B0), and generates three outputs: G, E and L. The output G (Greater) is set to '1' if A > B; the output E (Equal) is set to '1' if A = B; the other output L (Lower) is set to '1' if A < B.

Write a truth table of the binary comparator. Compile a K-maps for each output and write the expressions of the minimized synthesis of each output (synthesize them as two-level AND-OR networks). Draw the schematic of the resulting network, using (as a trace for the solution) the d-DcS schematic template provided here (click on the figure below):

Verify the circuit behaviour through a functional simulation and a timing simulation (a suitable test sequence is available in the Timing Diagram window).