Flip-Flops and Registers

Giuliano Donzellini, Domenico Ponta

Analysis of a Set-Reset flip-flop




Load the following Set Reset flip-flop schematic in the d-DcS, with a click on the figure:

Verify, using the timing simulation , the behavior of the flip-flop. You should represent all the possible combinations of inputs, using a proper time scale (a suitable test sequence is available in the Timing Diagram window).

Pay attention to include the special case where !Set and !Reset are both activated and then released (transition 0-1) exactly at the same time. Try to explain why the circuit shows a stable auto-oscillation, and why it can not happen in the 'real world'.