Introduction to FPGA and HDL Design

Examples    Exercises    Solutions    Errata corrige

9.1 Field-Programmable Gate Arrays

9.1.6 Deeds Support for FPGA

Pulse generator schematic (without FPGA configuration)

Pulse generator example: controller ASM diagram

Pulse generator schematic (configured for FPGA)

 

9.2 Introduction to VHDL

9.2.1 VHDL Code from Deeds

Click on the list below download the project files (generated by Deeds), as described in the chapter):

 


9.3 FPGA Prototyping Exercises

9.3.1 Synchronous Serial Communication System (8-bit)

Schematic template (without FSMs', without FPGA configuration)

FSM templates

            

9.3.2 Digital Chronometer

Schematic template (without FSMs', without FPGA configuration)

Controller ASM diagram template

Circuit block element (CBE) template

 


9.4 Solutions

9.4.1 Synchronous Serial Communication System (8-bit)

ASM diagram of the transmitter’s controller

ASM diagram of the receiver’s controller

Schematic (configurated for FPGA)

 

9.4.1 Digital Chronometer

Schematic ("circuital approach" CBE version, configurated for the FPGA board "DE0-CV")

The same circuit, but without FPGA configuration.

ASM diagram of the controller

CBE counter module ("circuital approach")

Schematic ("algorithmic approach" CBE version, configurated for the FPGA board "DE0-CV"). Note that the controller is unchanged, respect to the previous solution.

The same circuit, but without FPGA configuration.

CBE counter module ("algorithmic approach" version)

ASM diagram of the FSM enclosed in the CBE



9. Errata Corrige (Chapter 9)

Page 468

After the figure, read:

Page 469

After the figure, read: