Version 1.71.030 (Nov. 12, 2012)

   Deeds-DcS (Component Library, Schematic Editor)   

  A new "Push-button" input component has been added. It is useful, during interactive animation, to represent not only a real push-button device, but also to simulate pulse-shaped input command signals (i.e.: system reset).

  User can define, as a property of the component, if the button is "high" or "low" when pressed. The push-button is pressed with a mouse click; it is depressed when the mouse button is released. In the timing diagram window, the new push-button input track is defined as a usual switch input track.

  With the introduction of the new component, Switch and Push-button icons have been changed to highlight the differences between the two input components (in the main menu, in the component bin, in the timing diagram window and in the FPGA assignment window).

  Internal file version has changed (to 1.023), so files saved with the current Deeds version could not be opened in previous version. However, as usual, backward compatibility is maintained: current version can read all the previous version files.

  Bug fix: "demultiplexer" type components label have been corrected as "Dex 1 -> 2", "Dex 1 -> 4", "Dex 1 -> 8" and "Dex 1 -> 16".

  Bug fix: the "Rotate Component" buttons are now visible again (they disappeared from the previous version).

   Deeds-DcS (Timing Diagram)   

 Mouse wheel now controls the signal traces scroll up/down function.

 Bug fix: sometimes, closing the timing diagram window, the "focus" moved to another application, instead to go to the Deeds-DcS main window. The problem has been corrected.


  Version 1.70.112 (Sept. 29, 2012)

   Deeds-DcS (Component Library, Schematic Editor)   

 This version introduces a new library of components that replicates and enhances the previous one. The graphics of the new components shows a "3D effect".

 A drawing grid has been introduced (short-cut <ctrl>+G to show or hide the grid).

 The components belonging to the old library are displayed with the old look. Moreover, in a old file, the old components can be easily identified by activating the drawing grid: when the grid is on, the component is marked with a big red asterisk. This can be useful to manually update old schematics to the new library.

 The "3D effect" can be hidden (short-cut <shift>+G). This feature is useful to avoid a different look between new and old components when opening a schematic file saved with a previous version.

 A new "Test Point" component has been introduced; it displays, as a small rectangular LED device, the logic value of the wire to which it is connected. It is useful in interactive animation (it is not displayed in the timing diagram). Test points can be stacked together to visualize groups of bits.

 The step of the "internal grid" has been halved, the area available for schematics drawing is now twice as much. In comparison with the previous version it is now possible to use a drawing area four times larger.

 Now the drawing visible at video can now be zoomed to a very small scale.

 The command changing the sheet's format is now supported by the "Undo" system.

 Two new commands, "Zoom In" and "Zoom Out" are now available. The point chosen by a mouse click becomes the center of the enlarged (or reduced) new view.

 The former "Zoom" commands remain available: they can be activated, as before, with the short cut <PgUp> e <PgDn>. They enlarge, or reduce the view by reference to the center of the current one. When enlarging, the center of visualization is automatically moved to guarantee the visibility of the area used by the drawings.

 The mouse wheel now controls the "Zoom" function.

 A new "Panning" command is available. It works by dragging a point with the mouse: all the drawing translates with it.

 The new commands "Zoom In", "Zoom Out" and "Panning" are available in the context menu, too, and they can be used during simulation.

 A "View All" command, available in the "View" menu, has been added (short cut <Home>).

 Now, the current zoom level is saved with the circuit file: at the File/New, the zoom level is set to the "normal" value ("Zoom 5").

   Deeds-DcS (Simulation)   

 In the previous version, the asynchronous flip-flop did not update their outputs when Preset and/or Clear were released. This bug has been fixed.


  Version 1.60.100 (May 4, 2012)

   Deeds-DcS (FPGA Extension)   

 In this new release of Deeds, the "FPGA extension" includes the DMC8 microcomputer. The FPGA extension allows the compilation of a project into an FPGA chip starting from Deeds, leaving in the background the operations performed by the FPGA-specific EDA tool. The digital system exported in the FPGA may be composed of all Deeds' combinational and sequential components, any number of Finite State Machines and a DMC8 microcomputer.

 On the FPGA, the DMC8 microcomputer can be configured with a simple debugger that allows the step-by-step execution of the programs. If the FPGA board is equipped with an alphanumerical display, the debugger allows the visualization at run time of the processor register contents.

 Bug fix: the "ClockScaler" was not working properly for frequencies higher than 10 MHz.

 The Push Button in the FPGA board can now be set either "high" or "low" when pressed.

 Added support for the Altera DE2-115 board.

   Deeds-DcS, Deeds-FsM, Deeds-McE   

 Bug fix: in the previous release 1.5, when a tool main window was minimized, and then another instance of the same tool opened, the new instance was placed and sized out of the screen coordinates and it was impossible to see and restore it. The only way to recover from this situation was to delete some keys in the System Register. The problem now has been corrected.


  Version 1.50.015 Beta (Feb 13, 2012)

   Deeds-DcS (FPGA Extension)   

 This new release of Deeds includes a newly developed feature, named here "FPGA extension", specifically conceived for introducing FPGA-based systems in a course of digital design. This extension allows the compilation of a project into an FPGA chip starting from Deeds, leaving in the background the operations performed by the FPGA-specific EDA tool. In the present release, the extension allows to download in a FPGA board a digital system composed of all Deeds' combinational and sequential components, and any number of Finite State Machines. The inclusion of the DMC8 microcomputer is in an advanced state of development and it will be part of next release.

 Beginner users need to be familiar only with Deeds, with no knowledge of HDL and they do not interact with the FPGA tools except for the guided, almost automatic, FPGA compilation. As a result, we achieve a seamless integration between a Deeds project and the FPGA and therefore the possibility to configure an FPGA without necessarily going through the complexity of the full process. It is always possible, for more advanced user, to interact directly with the FPGA tools, having a full control of the design, simulation and compilation of the project.

 In the "File" menu of the Deeds-DcS, two new commands are available: "Export in VHDL" and "Test on FPGA".

 The command "Export in VHDL" opens a dialog window and, at the same time, starts the VHDL conversion of the file currently opened in the schematic editor. At the end of the conversion, the user will find one or more VHDL files opened in the multi-folder dialog window. All the VHDL files are automatically saved in a subdirectory (for instance, if the original file is named "Counter.pbs" and it is located in the directory "D:\Circuits\", the new subdirectory containing the VHDL files will be created as "D:\Circuits\Counter_VHDL\"). Note that this command is useful to reuse the VHDL code in another project, but it doesn't prepare directly files for FPGA implementation, as the other command does.

 The command "Test on FPGA", instead, opens the "Test On FPGA expert window" that allows to choose a commercially available FPGA board and to associate all the Input / Output of your Deeds schematic to the board devices and resources. In this release, two boards are supported: the DE1 and DE2 models by Terasic, based on an Altera Corporation FPGA.

 After the choice of the FPGA board, the user implements the associations by selecting (on the left hand side) each Input or Output termination and (on the right hand side) selecting a corresponding device available on the board. The highlighting of the selected objects in the Deeds schematic and in the board image will help in this process.

 Devices available are: switches, push buttons, leds, hex displays, and connectors. The on board clocks are internally "scaled" to various frequencies, so that the user can choose the frequency for each clock generator in the Deeds schematic. In the expert, commands to Undo/Redo and Lock the associations are provided.

 The button "Assignment Summary" allows to display a table reporting all the associations between Deeds project and FPGA board.

 The button "Generate Project" will produce the VHDL code and project files for the FPGA board. At the end of the process, it will prompt the user to launch the specific FPGA CAD, that should be previously installed ((i.e. for Altera FPGA, Quartus II "web edition", available for free from Altera Corporation website).

 The user instructs the FPGA CAD to compile the project and load it in the FPGA Board, ready to be tested.

 Note that all library components and Finite State Machines are exported in behavioral VHDL, while the top level schematic is compiled in structural VHDL.

   Deeds-DcS (schematic editor)   

 In the "File" menu, the list of most recently open files has been moved under a sub-menu, to reduce the overall vertical space required.

 The step-by-step button operations (of the micro computer simulation) have been fixed. Before, when a break point was encountered, the state of the button was not modified appropriately in accord with the new situation.

 When closing the Deeds-DcS, with the debug window opened, sometimes an error could occur. The error has been fixed (the debug window now is closed before closing the main application window).

 A new component, a Parallel Input Parallel Output (PIPO) register, had been added in the component library.

   Deeds-DcS (timing diagram)   

 Bug fix: in certain versions of Windows O.S., at the opening of the Timing Diagram Window, all signal traces resulted collapsed on the first one. Previously, this required scrolling the traces vertically down and then up.

 Bug fix: previously, when moving or resizing the Timing Diagram Window, sometimes the traces were drawn incorrectly, with missing lines.

 Bug fix: previously, in the redrawing of the Timing Diagram Window, sometimes the figures showing the time measurement between the "time cursors" disappeared. The font size has been increased.

 The short cut "F8" (in the Timing Diagram Window), permitting to switch to the main window, has been eliminated. Now, the Timing Diagram Window is always "on top" the main one, and cannot be minimized or maximized, but only moved or resized.

 A command "Close Timing Diagram" has been added to the Timing Diagram Window, in the menu opened by the upper left button of the command bar.

 Bug fix: the tracks of Hex Display, Dual Hex Displays, and 8 Led Array, when representing unknown signals at least on one sub-tracks, displayed '00h' instead 'XX' (unknown numerical value) on the main track.


  Version 1.20.101 (Feb 4, 2011)

   Deeds-DcS (schematic editor)   

 A new command allows to select an entire set of connected segments. The new command is available in the context menu (as "Select the Net"). It can be activate also with a <ctrl> + Click of the mouse over a wire segment.

 A new command has been introduced: "Duplicate". It is available in the Edit menu and in the context menu. This command behaves as a Copy, followed by a Paste, but it does not use the clipboard, so the clipboard contents will not change. This new command speeds up some kind of copy and paste operation, for instance when the user draws a wire between two pins of two different components and needs to duplicate it many times (one for each couple of pin to be connected).

 At the end of simulation, a bug caused that the circuit in the editor was not always repainted. This problem, born with version 1.01.031, has been fixed. Now all input and output components return to their "initialization state" when simulation stops.

 Decoders 2-4 e 3-8 have been fixed: their enable input, that is active "high", now has been drawn correctly (without the negation circle, and as "EN").

   Deeds-DcS (timing diagram)   

 With the new release the microcomputer instruction step simulation, formerly available only in the editor window in animation mode, is available in the timing diagram.

 The new step by step commands (the triangle-shaped buttons on the left of the traces) allows a fine control of the timing simulation. The button context menu sets the simulation advancement according to the nature of the chosen trace. For instance, for an input switch o clock, advancement could be set to: a) next edge, b) next rising edge, c) next falling edge. If the trace represent the microcomputer activity, the feature allowed is the instruction step.

 The new "Magnifier" allows the enlargement of the time scale in a portion of the diagram, chosen by the user by means of a couple of cursor. The magnifier is activated by a button on the view bar. When activated, the enlarged area is highlighted with a different background color.

 The new "View Bar" collects all commands that control the diagram views (Time Left/Right Scroll, Zoom In/Out, etc.). A View Navigator is available, appearing as a couple of arrows button (left side of the view bar) that control undo/redo of view related commands, by moving back and forward in the view history list.

 A new window area, activated by the "Activate Value Cursor" button, displays the "values" of the signals versus time. By moving the Value cursor, the user can choose the trace and the position on time. The representation on the "value" window area depends on the nature of the data themselves. Especially useful to follow the instruction sequence when tracing the execution of a microcomputer program.

 Every trace can be expanded vertically ([+] and [-] little buttons on the left hand side of a trace.

 The signal editor now allows command Undo/Redo (addition/deletion/moving of edges).

 The edge deletion command now stays active, allowing cancellation of more than one edge without the need of entering the command again.

 Now, the tracks of the Hex Display, the Dual Hex Displays, and the 8 Led Array can be expanded in sub-Tracks (as the Input Switch Array in the previous version).

 Now time measurement cursors, if already placed, remain visible when the user deletes timing diagram simulation results.

 Re-initialization of simulation has been fixed: the current view is maintained, and the "simulation stop" cursor is moved in the current view, if it is not already visible.

 When a "New Simulation" or "Load Input Sequence" command is entered, the system always warns that the previous simulation results will be lost.

 Sometimes, closing the timing diagram, a "List out of Bound" error occurred, especially when the user tried to close the window with a click on the Start Animation button (in the Main Window): this error has been corrected.


 With the release 1.01.31, the scroll bars in the ASM diagram editor disappeared. The problem now has been fixed.


 The bug of the "JP (HL)", "JP (IX)" and "JP (IY)" instructions (wrong jump destination) has been fixed.

 The bug of the "ADC HL,ss" and "SBC HL,ss" (wrong flag setting ) has been fixed; also fixed the "ADD IX,pp" and "ADD IY,rr" instructions.

 The Deeds-McE short guide has been updated.


  Version 1.01.031 (Jan 23, 2008)

   Deeds-DcS, Deeds-FsM, Deeds-McE   

 The learning material on the Deeds web site has been updated to be used with the present release. It is no more necessary to use the learning material inside the Deeds browsers: it is now possible work with the Deeds exercises opening them from the MS Internet Explorer or Firefox browsers, assuming that the Deeds package has been correctly installed on the user local machine.

 The current release has been tested under MS Windows Vista, and a few minor bugs have been fixed.

 The current release has been tested for compatibility with the Moodle content management system.

   Deeds-DcS (schematic editor)   

 A graphic bug in the schematic editor has been fixed: input and output signal names of Finite State Machine components are now correctly drawn.

   Deeds-DcS (timing diagram)   

 The warning messages produced by the simulator have been modified. Now, the message window reports, on the same line: 1) the message number, 2) the simulation time corresponding to the message, and 3) the message string.

 The internal ID of components are no more displayed in warning messages. Instead, when the user selects with a mouse click the message of interest, the related component or netlist is highlighted (selected) in the schematic editor.

 Moreover, in the timing diagram, when the user selects a warning message (if any), the "Home" cursor is moved (and the diagram panned) to the reported event time.


 The Deeds-McE file format have been updated to support the current release and to support FireFox browser.


  Version 1.01.030 (Nov 28, 2006)

   Deeds-DcS (schematic editor)   

 Added a "Frequency Multiplier" to the ToolBar. When the animation clock is active, the button allows to multiply the animation frequency by 1, 10 or 100. The resulting frequency range is now 0,5 .. 2500 Hz.

 As a result of the latest Windows updates, a new bug came out: when opening a ".pbs" or ".fsm" file in the respective environments, sometimes "file error" dialog message appeared; a subsequent attempt succeeded. This bug has been fixed.

 Changing the initial value of a Dip-Switch affects not only the traces of the single bits but the HEX trace too, as it should happen. In the previous release the graphical update of the HEX trace did not happen.

 In the animation mode a break point in a DMC8 would stop the clock animation but the "instruction step" button did not appear in the "object code" window. This bug has been fixed.

   Deeds-DcS (timing diagram)   

 Now the timing diagram visualises correctly the repeated execution of the same instruction (typical example LOOP: JP LOOP), while before it was not possible to see the transitions between one execution and the other.

 In the incremental simulation mode, when simulation results are cleared, now the system informs (correctly) the user that the simulation results will be lost.

 A button to lock and drag the end simulation cursor is now available, without the necessity of finding it in the diagram (a task not always easy, requiring sometimes a change of time scale).

 A new "View All" button has been added. It re-calculates time scale and horizontal diagram scrolling to fit all the signal transitions into view.

 At the opening of the timing diagram window, and when activating the New simulation command, the time scale and the end simulation cursor are set to default values, that the user can obviously modify.

 Now, when loading a input test sequence, the end of simulation time (and hence the cursor) is set automatically to the last edge of the input plus a fixed ratio of the simulation window width. The time scale, too, is selected in order to show the whole sequence from zero to the simulation end cursor.

 Now, when clearing the simulation results, the end of simulation cursor is repositioned to the previous simulation end time.

 A "Home Cursor" is now available. To activate it, a new button has been added. When the button is pressed, you can drag and place the new "Home Cursor" all over the diagram. Pressing again the button will hide the cursor.

 When the Home Cursor is active, the Zoom command will work centred on it; when hidden, the Zoom will act as before, i.e. centred on the left most time of the diagram current view.

 When simulation results are cleared, the Home Cursor is maintained on its previous placement, if active, so that the user could use it as a place holder.

 In the button pan bar, on the lower side of the window, a new button has been added to pan the diagram to the Home Cursor, if active.


  Version 1.01.026 (Oct 18, 2006)


 A few bugs have been fixed.


  Version 1.01.020 (Oct 3, 2006)

   Deeds-DcS (schematic editor)   

 The DMC8 Micro Computer Board component has been now released. It provides the functionalities of the micro computer based on the 8 bit microprocessor DMC8, already emulated by the Deeds-McE tool. While the latter allows to write and interactively debug an assembly program, it is now possible to insert in the Deeds-DcS schematic editor the DMC8 Micro Computer Board as a component. The board ROM memory can be loaded with the code developed with Deeds-McE. With this version is therefore possible to design and simulate a digital system composed by random logic, finite state machines and microcomputer boards.

 The new component Input Dip-Switches makes available eight input switches in a single device. It is especially handy with the micro computer board. The input values are shown as HEX numbers in the timing diagram main trace, and as binary in the eight sub-traces.

 Two new output devices, an eight LED array and a two digit HEX display, again useful with the microcomputer board.

 The components bin includes now an Interrupt Timer, available among the counters. It is based on a programmable 32-bit counter, and it is specifically conceived to be used with the microcomputer board, to generate periodic interrupt requests. A dialog box, activated from Interrupt Timer context menu, allows to define the timer cycle. The timing diagram, during the simulation, shows the Interrupt Timer internal state.

 A new component, the Text Box, allows the insertion of comments in the schematics. The Text Box (right end side on the component bin) is treated as any other component and can be moved, resized and edited with the help of a dialog box. The latter, available from the context menu, allows the editing not only of the text but also of the graphic appearance of frame and background. An arrow originating from the text box and pointing to a component can be set (the arrow is visualised only when the mouse moves over the text box).

 The components bin has been modified to host the new components. Now, the input and output devices are grouped in two sub-menus activated by the two left-most buttons.

 A double-click on a component of the schematic activates now its property window, if available. The window is the same as the one activated by the context menu. The double-click feature can be disabled by the user.

 The graphic appearance of the components is improved, especially for the Input and Output devices. At the same time the print quality is enhanced, allowing to exploit the full printer resolution.

 The new command Save Image of the File menu saves the circuit image (.BMP or .PNG format). The dialog window offers the option between "Web Quality" and "Print Quality" and allows to set magnification and resolution. An image preview is available. The new feature lends itself very well to generate quality images for web pages or printed materials.

 A few bugs related to error warning in the "animation" mode have been fixed, in particular the incorrect stop of the simulation in case of error. Also, now, the "New" and "Load File" commands remove correctly the warning window.

 The Windows print spooler now shows correctly the file name of the circuit. In particular, when printing a circuit to which no filename has been assigned, the print spooler displays "Unnamed".

 The selection rectangle now has eight grips, instead of the former four.

   Deeds-DcS (timing diagram)   

 The timing diagram shows major improvements, as a result of the addition of a database of input sequences that can be saved, loaded, deleted and modified. Formerly, input sequences had to be redrawn each time the timing diagram window was opened. In the current version, a sequence can be saved (with a name) inside the same .pbs file of the schematic and, therefore, applied to the circuit as many times as necessary, also after schematic modifications. Another advantage is the fact that a circuit can be delivered with suggested input patterns for demonstration or other purposes. The commands of the input sequences database are collected in a button in the farther left position of the timing diagram toolbar.

 Enhanced input signals editor with facilities for defining multiple inputs, as in the "Dip-Switch" component. The single bit tracks are edited one at the time and the corresponding collective HEX track is updated on the fly.

 The new commands Move on Top and Move to Bottom perform their action on a trace of the timing diagram. They allow a faster rearrangement of the traces, by respect to the already available Move Up and Move Down. All the above commands have shortcuts activated by the keyboard (Home and End for Move on Top and Move to Bottom, Arrow Up and Arrow Down for Move Up and Move Down), active on the track button the mouse pointer is positioned over.


 The updated Assembler now supports the directives DB (Define Byte) and DW (Define Word) to load in the ROM memory numerical constants, characters, strings.

 The EQU and ORG directives can have as argument a previously defined symbol.

 The Assembler message system is now more extensive and precise.

   Deeds-DcS, Deeds-FsM, Deeds-McE   

 Now the Deeds Main Browser accepts command line parameters. So you can launch the Deeds and automatically open a web page in it, as specified by the command line. The HTML file can be renamed as .DHP (Deeds Hypertext Page), enabling the operating system to recognize this page and launch it in the Deeds Main Browser, instead of in the default web browser.


  Version 0.99.995a Beta (03 - 10 - 2005)

   Deeds-DcS (schematic editor)   

 The component library has been enhanced. All the logic gates, previously with 2, 3, and 4 inputs only, are now available in the new 5, 6 and 8 inputs version. For this reason, the version of ".pbs" files has changed; old files are read by the new version, while files created by the new version are nor read by the older ones.

 It is now possible, in the 'Interactive Animation' mode, to activate automatically the Clock generators. The automatic "pulsing" of the Clocks can be activated and controlled by a button and a cursor added to the main toolbar. The cursor controls the effective animation frequency in the range 0.5 Hz through 25 Hz, independently of the setting of the "nominal" clock frequency. If more than one Clock is present, the cursor controls the one with the highest frequency, while the other Clocks will be animated with a timing reflecting proportionally their frequency relations.

 When loading a ".pbs" file saved with a previous Deeds version (until 0.99.993d included), it is necessary that the files ".fsm" of the Finite State Machines used in the circuit will be present in the same directory of the ".pbs" file. The old format file is converted internally, and the ".fsm" file is included (embedded) in the ".pbs" file. A bug in this conversion process has been fixed. Now it is possible, as expected, to delete a Finite State Machine component, edit its ".fsm" file and re-load it in the circuit. Before the fix, this bug compelled the user to rename the original ".fsm" file.

 Now, Input /Output components allow a mixed form of the signal name. For instance, if you assign to a signal the name "Down/!Up", in the editor it will be represented as the word "Down/" followed by the word "Up" with an horizontal line over. Obviously, the traditional naming mode of signals is maintained: for instance, the word "!Pippo" will show up as "Pippo" with a line over. Only the first "!" in the string is taken in count, and all the chars following it will be represented with the line over.

 Now, in the properties window of FSM components, you can read informations about the original ".fsm" file that was loaded as component (name, date, time and dimension of the file).

 The symbol of the universal register components (Univ2, Univ4,Univ8) has been fixed. The input names 'R-In' and 'L-In' have been exchanged. The functionality of the component has not changed, however ('L-In' is the serial input for the left shifting mode of the register and it is represented on the right side; 'R-In' is the one for the right shift, and it is placed on the left side).

   Deeds-DcS (timing diagram)   

 The timing simulation loop has been revised and optimized. Now the time duration of a simulation is proportional to the chosen simulation time interval. This solves the problem of excessive waiting times in the case of simulation with a long time interval. The progression of the simulation is correctly displayed on the status bar (as percentage of the total time interval), and the diagram regularly updated to show the current simulation status.

 Now, the user can interrupt a simulation, by clicking on the "Stop" button. This feature is particularly useful for long simulation intervals. The user will be prompted with a dialog box.

 If the user attempted to close the timing diagram window during a 'long time' simulation, an 'access violation error' occurred. Now the problem has been fixed: the user will be prompted with a dialog box and simulation can be halted. Then, the user will be able to close the window correctly.

 The "Delete Edges" command removes, by default, one edge (if it is the last edge), or a pair of edges (if made between two existing transitions). Now, if it is necessary to delete more edges, the user can press the keyboard "control" button when deleting: in this way, the command is not cancelled immediately, allowing to continue operations without the necessity to restart the command.

 In the timing diagram, during editing of input signals, sometimes an 'access violation error' occurred: the problem has been solved.

 The timing window toolbar can not be hidded anymore, as long as that bar is necessary to use the timing diagram functionalities.

 The context menu to configure the tool and the status bar can be activated, now, also from the signal buttons panel (the panel on the left), with a right-button mouse click.


 The last sub-version introduced a major bug: during debugging, the execution of certain instructions hanged up the emulation engine. The bug, due to errors in the internal instruction code table, has been fixed.

 Now, when you exit the Animate execution mode (pressing the "pause" button) the PC field is correcly re-enabled, as expected.


  Version 0.99.994b Beta (15 - 04 - 2005)


 In the timing diagram, painting of the trace of a binary signal showed an anomalous ramp if a 'unknown' level followed a 'zero' level: this problem has been fixed.


 ASM diagrams created with the previous version could contain errors in state coding. It happened when the user, for some reason, decided to reduce the number of state variables. As a conseguence, state codes could be corrupted. The error was invisible to the error checker of the d-FsM, so simulation of a FSM containing this problem failed. Also, Deeds-DcS did not refuse the corrupted FSM's, so simulation in Deeds-DcS failed too. Now the error has been fixed, so a newly created file behaves correctly. Old corrupted files are automatically corrected when loaded in the d-FsM editor, and the user is warned. However, due to the nature of the error, in some case the user will need to adjust state codes (i.e., the automatic correction could produce duplicates of state codes). After the necessary adjustments, the user must overwrite the old .fsm file. Also, if the FSM component has been previously loaded in a Deeds-DcS schematic, it must be deleted and reloaded in the Deeds-DcS, in order to fix the .pbs file.

 State code button graphics, in the "property editor", have been fixed, so that buttons' graphic do not look corrupted anymore.


  Version 0.99.994a Beta (01 - 04 - 2005)

   Deeds-DcS (schematic editor)   

 The version of ".pbs" files has changed: old files are read by the new version, while files created by the new version are nor read by the older ones.

 In the schematic editor is now available a "context menu", that includes some among the most used commands, and other ones, function of the click point.

 The "Labeling Tool" command has been substituted with the "Properties" one. This command allows not only the editing of component labels but also to set the simulation initial values for "Input" and "Clock" blocks. It allows to define also the work frequency for "Clock" components.

 "Copy Image" now saves on the clipboard the whole circuit as a bitmap image, without the need of selecting it. The command is now available also during simulation.

 "Copy": now saves on the clipboard not only the bitmap image of the selected area of the circuit but also the proprietary format.

 "Cut","Copy" and "Paste" work within the same circuit or into other instances of Deeds-DcS.

 Unlimited "Undo" for all editing operations.

 Improved component selection: a single component is selected with one click, showing the selection rectangle around it. The position of the vertex of the selection rectangle can be modified through the 'grips'. <Shift>+click on a component or a wire adds it to the selection or removes it.

 The "Move" command is not present in the menu anymore. Selected objects can be directly dragged to a new position, with automatic disconnection and reconnection of the terminals.

 Now nodes can carry up to four connections, instead of three. It is possible now to connect more than one wire on a component pin. Two pins, though, must be connected by a wire.

 FSM inserted on the circuit are no more linked but embeddeb in the "pbs" file, that now contains all circuit information. As a consequence, if the original FSM file is modified, it is necessary to delete the old FSM component from the Deeds-DcS schematic and reinsert the modified one. An old file, if saved in the new format, will embed the FSM components.

 Improved circuit error check. The "Error Check List" command performs a test of the circuit netlist and shows the list of warning and error messages at the bottom of the editor. By clicking on a single message, the fault is highlighted.

 Automatic circuit error check before the beginning of simulation avoids most error messages from the simulation engine. The simulation is not launched if errors are present.

 A "Component Info" button is now available to show, by clicking on a component placed on the schematic, its type and internal identifier.

 Now it is possible to print the schematic when simulation is running. The printout will show the state of the input/output components, as they are in that moment. Same behaviour for the command "Copy image".

 Now, when printing the drawing through Adobe Acrobat printer driver, the "pdf" file is created correctly, and the editor window contents are no more corrupted.

 A little "graphic" bug has been removed. When you load a FSM component from file, the 'dragging' of the FSM symbol should be now clean, without spurious images.

   Deeds-DcS (Timing Diagram)   

 A new button has been added, at the left of each "signal button". The new button controls the highlighting of the signal edges (by displaying vertical dotted lines).

 By clicking on the signal button, it is now possible to expand the FSM trace into a multiple trace, showing all the FSM signals. The choice of the signals appearing in the multiple trace has to be made, before simulation, with the dialog box appearing when clicking the FSM signal button (see the "Select Signal to Trace" command).

 The signal vertical ordering (that the user can modify) is now saved with the file, as well as the choice of the signals appearing in the multiple traces.

 The new command "Clear Simulation" allows to start again the simulation without losing the former input stimulus sequence, which can be edited. The "Restart Simulation" command, instead, is similar to the "Clear Simulation" one, but it also clear completely the stimulus sequence.

 Stimulus signals can be edited now independently from the position of the "Simulation Stop Cursor": now it is possible to prepare a long input sequence and then simulate it progressively.

 The input signals editor has been improved with two new commands: "Edit Edges" e "Delete Edges". They replace the former "Add Edge".

 "Edit Edges" allows to insert new transitions and to move existing ones. Moving the mouse over the trace being edited, a preview of the change is shown.

 The change may consist in: a) the insertion of a new edge (if made after the last edge) or b) the insertion of a pair of edges, forming a pulse (if made between two existing transitions). When the mouse points an existing edge, the edge itself is highlighted, to indicate that it can be dragged to either direction.

 "Delete Edges" removes existing edges. Moving the mouse over the trace, a preview of the deletion is shown.

 The change may consist in: a) the deletion of one edge (if it is the last edge) or b) the deletion of a pair of edges (if made between two existing transitions).

 A time measurement command allows to place two vertical cursors ("I" and "II") everywhere; the user can move, hide and reposition the cursors with the mouse. The time measurement is reported directly on screen, between the two cursors.


 Now, when printing the drawing through Adobe Acrobat printer driver, the "pdf" file is created correctly, and the editor window contents are no more corrupted.


 The ORG directive has been fixed. Now it is possible to declare ORG addresses without restrictions. Before it was necessary to place them in order (by growing address).

 Now the break points can be toggled also in the object code grid, not only in the source code editor. The break point can be toggled also when animation is active (at run time). To toggle a break point, you can 'right' click over a line of object code, choosing the appropriate context menu item. The break point can't be set if the line does not correspond to a valid line of code.

 The emulation "engine" has been revised and optimized, allowing a faster emulation.

 The new "RUN" command allows to execute the program at the maximum speed allowed by the PC in use. When running, the user can interact with the board only by means of the input and output ports. The register contents are hidden, but the clock cycle counting shows the activity of the processor. The processor can receive Reset and Interrupt request, and execution can be stopped on break-points, if defined by the user. Execution can be paused manually.

 Now, the "Step by Step" command executes always a single instruction, except when the "Over" button is down. In this condition, if the instruction to be executed is a CALL, the execution will flow in "Run" until the instruction following the CALL will be reached by the program execution. With this new functionality, the user can execute the program at an "high" level.

 In the debugger window, a new frame, named "Info", informs the user about run-time errors occurring during program execution. This area collects all messages and substitutes the previous method to show messages by means of a dialog box. The messages can be cleared and/or saved as text on the clipboard.

 The memory frame has been enhanced. Now it is possible to edit the memory contents also in the "ASCII" side of the window.

 The PC edit field of the register panel has been substituted with a "drop down" list control, so that its value can't be changed randomly anymore. Now, only valid instruction addresses can be chosen as PC value.

 A printing bug has been fixed: now, printed pages show a little white margin around, as expected.

 The bug of the vertical scroll of the editor has been fixed: now the break point bar, on the left of the editor, scrolls correctly, following all the editing operation of the user.

 To avoid ambiguity during debugging, the multi-page code editor has been reduced to a single file editor. Now, if it is necessary to open more than one file at the same time, simply launch the number of instances of the micro-computer emulator that you need, and open and emulate each file separately.

 Now, the "Force Program Counter" menu item, accessible from the object code grid, is displayed only if the selected line corresponds to a valid line of code.

 When switching between "Extended" and "Compact" Object Code display mode, the selection of the object code line is maintained (if it corresponds to a valid line of code).

 Sometimes, in the object code grid, invalid address labels were displayed. The problem has been fixed.


  Version 0.99.993d Beta (20 - 01 - 2004)


 It has been solved a bug of the "Save As" command: now, if you press the 'Cancel' button of the 'Save As' standard dialog, the Close operations, if running, are aborted as expected.

 The execution of the RRCA instruction has been fixed.

 The "I/O Port Address" dialog, on computers with the video card configured in a low-resolution mode, did not appear. The problem has been fixed, the dialog now will show always (centred on the main window).

  Version 0.99.993c Beta (11 - 11 - 2003)

   Deeds-DcS, Deeds-FsM, Deeds-McE   

 Now, when a new version of the Deeds is installed, the browser home pages are reset to the defaults, to avoid confusion between the different Deeds versions. However, the address of the previous user home page is not lost: it will be found in the history list of the opened pages, in the 'open' window.


 An error in simulation of finite state machine components has been fixed (the behaviour of the network when the FSM Reset input is activated at time=0).

 Now, when you start the 'interactive' simulation, the input switches are initialised according to the assigned names: as in the 'timing' simulation mode, the initial value will be set to 'one' if the name represents an 'active low' signal (i.e. the name is negated). As a consequence, for instance, all the components that require a (low activated) reset now will start un-initialised, showing 'unknown' outputs until the user will reset them expressly. When you exit the 'interactive' simulation all inputs an outputs reset to their default status.

 Now, during the 'timing' simulation, the circuit in the editor shows input and output value coherently with simulation results. You can observe the input/output status of the circuit in the editor before and after each simulation step.

 Now, when you print the circuit, or copy it as image on the clipboard, the resulting picture is coherent with the input/output values urrently displayed in the editor.

 The maximum time for simulation has been fixed, now it is no more limited to 32678 nS.


 Now, when timing simulation window is iconized and the simulation closed, the bar buttons are correctly enabled and updated.

 Now, when editor and timing windows are in iconized or maximized state, and the user closes them, their 'normal' position, instead of the currently one, is saved. In this way, when the user will re-open the windows, these will be placed in their 'normal' position. The correction has been done to reduce flickering and flashing of the windows on the screen.

  Version 0.99.993b Beta (04 - 11 - 2003)


 An error in simulation of the decoders has been fixed.


 In the debugger OBJECT CODE frame, the memory 'extended view' command has been fixed: now, in this mode, all the micro-processor memory space is shown.

 The ASCII table page, in the On Line Help, has been corrected.

  Version 0.99.993 Beta (15 - 10 - 2003)


 A new simulation tool has been added to the Deeds: the Micro-Computer Emulator (Deeds-McE).

 The functionally emulated board include a CPU, ROM and RAM memory, parallel I/O ports, reset circuitry and a simple interrupt logic.

 The custom 8 bit CPU, named DMC8, has been designed to suite our educational needs, and it is based on a simplified version of the well-known 'Z80' processor.

 The Deeds-McE integrates a Code Editor, an Assembler and a machine-level interactive Debugger.

 The integrated source code editor enables user to enter assembly programs, and a simple command permits to assemble, link and load them in the emulated system memory.

 The execution of the programs can be run step by step in the interactive debugger, where the user can observe all the structures involved in the hardware/software system

 By now, the integration of this tool with the Deeds is not complete: the board can not be inserted in the Deeds-DcS (yet).


 The simulation kernel code has been completely revised, and its code linked with the executable. The current version doesn't need the installation of the ActiveX that the previous versions do, and some mistake in the simulation of complex components has been fixed.

 The 'Delete' (by Selection) command has been fixed.


  Version 0.99.991 Beta (11 - 07 - 2003)


 Now the d-FsM tool can export the finite state machine in VHDL format. The command is available under the 'File' menu item. The user can view the VHDL code, copy it on the clipboard, or save it on a text file ('.vhd').

 The 'State at Reset' is highlighted with a little diamond, placed on the top-left of the state block. A 'starting' state block is now accepted (i.e., a state without a connection over it, normally used as 'State at Reset', or to drive the FSM, through the unused states, to a 'safe' state).

 The graphic editor has been radically modified. Now blocks and lines can't be inserted or moved over other blocks and lines: this is highlighted in the editor by displaying a red 'denied' signal when appropriate.

 The 'selection' rectangle is now re-sizable, 'grip points' are available to move the four vertexes with the mouse.

 Now it is possible to show/hide the 'drawing grid' (the command is under the 'View' menu item).

 In the editor the user can use the new Zoom commands; they permit an easier editing of the ASM diagrams (the commands are under the 'View' menu item and on the toolbar).

 A new feature of the editor permits the controls of insertion, moving and editing of lines. This feature automatically breaks (or links together) the lines, as they are inserted, moved or edited. The criteria are to connect line segments only on their vertexes. In this way all the previous bugs, related a 'lateral' ('T' shaped) connection between lines, have been fixed.

 The algorithm that automatically assigns the code to a 'newly created' state has been modified. Now it assigns to the state the first not-used code (checking it from the lowest code available). If no state is deleted, this mode of operation is equivalent to assign codes in up-order. If a state is deleted, its code will be re-used. If a code value is no more available, the user, when trying to insert a new state block, is prompted to add another variable to the state register.

 During insertion, moving or editing of ASM blocks and lines, if the user presses the <escape> key, the current operation is automatically aborted.

 The <delete> key now acts on the 'key-down' instead of the 'key-up' (conforming its behaviour to all the Windows application).

 In the IN/OUT dialog, pressing the <Return> key generates no more a tedious beep; also, in the same dialog, it is now possible to edit, as expected, the eighth Input (or Output) entry.

 Now it is possible to design a FSM having no input signal (for instance, a simple binary counter).


 In the previous version, a click on the 'Cancel' button of the message dialog that appears when you want to create a new Finite State Machine hanged the Deeds-DcS. The problem has been fixed.


  Version 0.99.990b Beta (13 - 05 - 2003)


 'Cascade' connection of more than two conditional blocks do not hang the program anymore: the bug has been fixed. Now the program seems also to process correctly conditional blocks connected in a 'nonsense' mode.

 Some algorithmic optimization has been done, so the program now is faster that before (during redrawing, when the diagram is 'big').

 The Properties window now shows correctly for all the screen resolution. Now the user controls its visibility and the visibility is remembered between work sessions.

 The In/Out dialog now remembers, between work sessions, which page was last opened.

 The timing window doesn't ask the user anymore, if no simulation has been started; instead, now the program prompts the user on a "clear diagram" request, if data could be lost.

 Drawing of output names, in the state and conditional output blocks has been enhanced. They are displayed from left to right, on two lines. If some output name can not be displayed, for lack of space, a '+' sign appears after the last one, on the second line, to notify the user that more output have been assigned to the block, but that they can not be displayed.

 Anyway, the complete output list is visible on the bottom status bar, when the user points the mouse over the block of interest.

 The algorithm that shows the arrows on the lines has been enhanced, and the arrow shape modified.

 Drawing of the input name in the decisional blocks has been horizontally centered.


 Drawing of input and output pin names, in the FSM components, has been enhanced. To avoid overlapping of 'long' names, names too long are shorted (at display level).


  Version 0.99.990 Beta (20 - 02 - 2003)

   Deeds-DcS, Deeds-FsM, Deeds-McE   

 The Deeds and Assistant browsers are now enabled and specialized to 'run' the Deeds learning material (as well ordinary HTML pages). During operation, these browsers decode the so-called Deeds Commands, that the author of a lesson (or laboratory session) include in the HTML page to enable interactivity between the HTML page and each Deeds tool included in the suite.

 Now it is possible to open a file downloading it from internet. This command is intended to be driven by the Deeds browser, when the user clicks on an active link, to open a file.

 Now, when a Tool is launched, the "Splash Form" is displayed only the firth time.

 The problem of 'double launch' of Deeds when you start it from the Application Bar has been solved.

 For debug reasons, a "hard close" command has been added. If could be necessary, you may close the Deeds main application (without closing also the other tools), activating the ordinary "File/Close" command while pressing the <Shift> and <Control> keys.


 Now the title of the Timing Diagram window shows the current timing simulation mode (the modes enabled are, by now: the Incremental Interactive Simulation mode [IIS], and the Timing Interval Simulation mode [TIS].

 Now it is possible to open a file downloading it from internet. This command is intended to be driven by the Deeds browser, when the user clicks on an active link, to open a file.

 The warning messages of the simulator, when needed, are displayed in a list at the bottom of the main window (if in 'animation' mode), or at the bottom of the timing diagram window (if in 'timing' mode). In this way the messages results more kind to the user than before, when each message was displayed by a dialog box.

 Now, the last status bar message can be displayed moving the mouse over the bar itself.

 In the Timing Diagram, the highlighting of the transitions of a specific signal has been enhanced. By clicking the button corresponding to a specific signal, you can toggle among four highlight modes: a) vertical lines on 0-1 transitions only; b) vertical lines on 1-0 transitions only; c) vertical line on all transition; d) no highlight.


 Drag and Drop of FSM files from the file manager has been enabled.


  Version 0.99.930 Beta (10 - 05 - 2002)


 Finite State Machine components, when not completed, cann't be loaded in the Deeds-DcS. This is OK, but under some circumstances, the user message explaining that the file wasn't completed didn't appear. This problem has been fixed.


 The Print command has been fixed, now it is possible to print on paper ASM diagrams.

 Some file/save file/open bugs has been fixed.

 The "Save" file commands have been completed with automatic file backup generation: for instance, before saving file "name.fsm", if a previous version of the file exists, this is renamed in "name.˜fsm".

 The File/Close command has been fixed: it no more operational if no file is opened.

 A known problem has not been fixed yet: under some circumstances, 'big' ASM diagrams can show a sensible slowing of window repainting.


  Version 0.99.920 Beta (22 - 03 - 2002)


 Now, in the schematic editor, labeling of the component is allowed only for Input/Output components. Attempt to label another kind of component results in a warning message on the status bar of the window. You can set a negation bar over Input/Output component labels placing a '!' on front of the label string. The editor accepts also a leading '/' or '\', but the '!' has to be preferred. Moreover, the negation bar is now displayed also on the signal name in the timing diagram window.

 Drawing of Finite State Machine components has been (partially) fixed for those components placed with "down" and "up" orientation. Before this fix, displayed name of inputs and outputs were not the right ones. Anyway, we suggest to not use "down" and "up" orientation for Finite State Machines, as name strings could easily overlap.

 In the Timing Diagram, now signal names are "buttons" evidenced by proper glyphs and colors, and negated signal are displayed up-lined.

 You can highlight the transitions of a specific signal with a click on its name button (in this way, you can relate its transitions with the behaviour of the network under simulation).

 If you click with the mouse right button on a signal name button, you activate a context menu. Context Menus allow to move up or down the signal traces and to set signal properties. For instance, you can change clock period and initial value for clock inputs, and initial value of the ordinary input signals can be set.

 In the Timing Diagram, activating simulation and/or signal editing without to release the "Time Stop" cursor is now inhibited, avoiding the bug of losing the cursor.

 Now the "F8" short cut not only sets the Timing Diagram Simulation mode, but also put the Timing Diagram window on the Top if already present. Instead, if the Timing Diagram window is on Top, the "F8" short cut gets the main window on Top again.

 The problem of redrawing of the vertical lines used as cursors in the timing diagram has been fixed (before, when "hint" messages of buttons were displayed and the mouse moved away through the diagram, some pieces of lines remained on the screen).

 When timing simulation is active, editing of circuit is now actually inhibited (the "out of bound" error has been eliminated).

 Now, before to simulate, the application asks the user for saving the file of the circuit, if the file has been modified.

 The internal "simulation loop" has been enhanced, making timing simulation faster.

 Now it is possible to break simulation when tired to wait for long times, by clicking on the Stop button. You'll be requested to confirm breaking.

 During long simulations, a percentage of the work is displayed on the status bar, at bottom.

 Finite State Machine simulation has been fixed and enhanced: now, at simulation start, their state is considered "undefined" until the Reset signal is activated, as expected. However, due to limitation of the model used, by now the outputs are considered always "unknown" until state stay undefined, without taking in count conditions from the inputs.


 Now it is possible to restore correctly the application windows after having closed them in the maximized state.

 Now, some commands no more generate errors when activated in absence of opened windows.

 Some error message revised, some others translated in English.

 The Print command has been disabled, waiting a major fix of the printing module.

 few minor bugs have been fixed.


  Version 0.99.910 Beta (01 - 03 - 2002)


 Added the ability to copy on the Clipboard the Timing Diagram current view.

 Now, in the Timing Diagram, you can highlight the transitions of a specific signal with a click on its button; in this way, you can relate its transitions with the behaviour of the network under simulation.

 A few bugs have been fixed.


  Version 0.99.900 Beta (22 - 02- 2002)

Released for internal beta test only.